Plurion Architecture
Soon Verilog hardware descriptions and a PDF file with documentation about Plurion® will be posted here.It is basically a set of RISC processors connected by ring networks.
It uses the RISC42 for each processor
See also:
- An out-of-date design paper
- The overall architecture is basically correct
- Neither the stack processor nor the IO processor are in the current design (both were replaced with RISC42)
- Email: Language Neutral Processors
- Email: RISC42 History
- Squeak's Threading Architecture