library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. library UNISIM; use UNISIM.VComponents.all; entity video is Port ( master_clock : in std_logic; leitor : in std_logic; probe : out std_logic; dac : out std_logic_vector(3 downto 0)); end video; architecture Behavioral of video is component spblockram is port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(8 downto 0); di : in std_logic; do : out std_logic); end component; Signal rstshft : std_logic_vector(31 downto 0); signal rst, md : std_logic; signal cnt : std_logic_vector(11 downto 0); signal vcnt : std_logic_vector(8 downto 0); signal seno, cor, fase : std_logic_vector(3 downto 0); signal corr_fase : std_logic_vector(31 downto 0); -- type mem1 is array (127 downto 0) of std_logic; -- signal barras : mem1; signal wbarras, obarras : std_logic; signal pbarras, abarras : std_logic_vector(8 downto 0); signal leitor_g, leitor_int : std_logic; signal CLKIN_w, RESET_w, CLK2X_dll, CLK2X_g, CLK4X_dll, CLK4X_g : std_logic; signal LOCKED2X, LOCKED2X_delay, RESET4X, LOCKED4X_dll : std_logic; signal logic1 : std_logic; signal LOCKED, CLK2X, CLK4X : std_logic; begin process (master_clock) begin if master_clock='1' and master_clock'event then rstshft <= rstshft (30 downto 0) & '1'; end if; end process; rst <= '0' when (rstshft(31)='1') else '1'; leitorpad : IBUFG port map (I=>leitor, O=>leitor_g); logic1 <= '1'; CLKIN_w <= master_clock; RESET_w <= rst; --clkpad : IBUFG port map (I=>master_clock, O=>CLKIN_w); --rstpad : IBUF port map (I=>rst, O=>RESET_w); --dll2x : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLK2X_g, RST=>RESET_w, -- CLK0=>open, CLK90=>open, CLK180=>open, CLK270=>open, -- CLK2X=>CLK2X_dll, CLKDV=>open, LOCKED=>LOCKED2X); -- --clk2xg : BUFG port map (I=>CLK2X_dll, O=>CLK2X_g); -- --rstsrl : SRL16 port map (D=>LOCKED2X, CLK=>CLK2X_g, Q=>LOCKED2X_delay, -- A3=>logic1, A2=>logic1, A1=>logic1, A0=>logic1); -- --RESET4X <= not LOCKED2X_delay; -- process (clk2x_dll) -- begin -- if (clk2x_dll='1' and clk2x_dll'event) then -- md <= master_clock; -- end if; -- end process; -- clk2x_dll <= md xor master_clock; -- clk2x_g <= clk2x_dll; clk2x_g <= master_clock; -- PARA PLACA COM 27MHZ!!! dll4x : CLKDLL port map (CLKIN=>CLK2X_g, CLKFB=>CLK4X_g, RST=>rst,--RESET4X, CLK0=>clk2x, CLK90=>open, CLK180=>open, CLK270=>open, CLK2X=>CLK4X_dll, CLKDV=>open, LOCKED=>LOCKED4X_dll); clk4xg : BUFG port map (I=>CLK4X_dll, O=>CLK4X_g); lckpad : OBUF port map (I=>LOCKED4X_dll, O=>LOCKED); --CLK2X <= CLK2X_g; CLK4X <= CLK4X_g; barras : spblockram port map (clk=>clk4x, we=>wbarras, a=>abarras, di=>leitor_g, do=>obarras); wbarras <= '1' when (vcnt(4 downto 0)="0001") else '0'; abarras <= pbarras+cnt(11 downto 2) when wbarras='0' else pbarras; probe <= corr_fase(31); process (leitor_g) begin if (leitor_g='1' and leitor_g'event) then leitor_int <= not leitor_int; end if; end process; seno <= "0000" when (fase="0000") else "0010" when (fase="0001") else "0100" when (fase="0010") else "0101" when (fase="0011") else "0101" when (fase="0100") else "0101" when (fase="0101") else "0100" when (fase="0110") else "0010" when (fase="0111") else "0000" when (fase="1000") else "1110" when (fase="1001") else "1100" when (fase="1010") else "1011" when (fase="1011") else "1011" when (fase="1100") else "1011" when (fase="1101") else "1100" when (fase="1110") else "1110"; -- frequencia na placa = 14.298.090 Hz, 4x = 57.192.360 -- fator de correção para 3.579.545 é 0,0625878176 -- em 32 bits: 268.812.630 (este numero foi alterado depois empiricamente) -- frequencia na placa atual = 27.000.000 Hz, 2x = 54.000.000 -- fator de correção para 3.579.545 é 0,0662878703 -- em 32 bits: 284.704.235 fase <= corr_fase(31 downto 28) when (cnt(11 downto 10)="00") else corr_fase(31 downto 28) + vcnt(6 downto 3); cor <= seno when (vcnt(2 downto 1)="00") else seno(3)&seno(3 downto 1) when (vcnt(2 downto 1)="01") else seno(3)&seno(3)&seno(3 downto 2) when (vcnt(2 downto 1)="10") else "0000"; -- seno(3)&seno(3)&seno(3)&seno(3); dac <= "0101" when (cnt(11 downto 8)="0001" and vcnt(8 downto 2)="0000001") else -- hsync in vsync "0000" when (vcnt(8 downto 2)="0000001") else -- vsync "0000" when (cnt(11 downto 8)="0001") else -- hsync "0101" when (vcnt(8 downto 5)="0000") else -- blanking vertical "0101" + (seno(3)&seno(3 downto 1)) when (cnt(11 downto 6)="001001") else -- color burst "0101" + (seno(3)&seno(3 downto 1)) when (cnt(11 downto 6)="001010") else -- more color burst "0101" when (cnt(11 downto 10)="00") else -- blanking horizontal -- "0111" when (barras(conv_integer(cnt(11 downto 5)))='1' and vcnt(8 downto 4)="00101") else -- bar code "0111" when (obarras='1' and vcnt(8 downto 4)="00101") else -- barras do leitor "1011" when (vcnt(8 downto 4)="00101") else cor + ((not cnt(10))&cnt(10)&(not cnt(9))&cnt(9)); -- color bars -- cor + "0101" + "0"&cnt(10 downto 8); process (CLK4X) begin if (CLK4X='1' and CLK4X'event) then corr_fase <= corr_fase + "00010000111110000110110111101011"; -- era "00010000000000000100000101010110" if (cnt="110101101000") then -- era "1110.0011.0100" cnt <= "000000000000"; if (vcnt="100000101") then vcnt <= "000000000"; else if (vcnt(4 downto 0)="0001") then pbarras <= pbarras + 1; end if; vcnt <= vcnt + 1; end if; else cnt <= cnt + 1; end if; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity spblockram is port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(8 downto 0); di : in std_logic; do : out std_logic); end spblockram; architecture syn of spblockram is type ram_type is array (511 downto 0) of std_logic; signal RAM : ram_type; signal read_a : std_logic_vector(8 downto 0); begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(a)) <= di; end if; read_a <= a; end if; end process; do <= RAM(conv_integer(read_a)); end syn;