Translation from part of a report to Unitron about the Turbo Mac project.
by Jecel Assumpcao Jr

page 1 is missing
------
page 2

... frequency, but with different phases and duty cycles. The most intuitive
way of understanding these sets is to consider them as indicating the
current state for a finite state machine.

[drawing with VIAPB6 and HSYNC waveforms]

Basic Cycle:

    We will call the interval between two successive loads of the video
register "the basic cycle". It was exactly this cycle that was changed,
such that all other changes were merely consequences of this. In the
original design this cycle was divided into two memory cycles: one
for the processor and the other for video. The change was the division
of the basic cycle into three cycles for the processor and one for video.
The timing of the basic cycle is the same: 16 cycles of the system clock
(SYSCLK) which is equivalent to 1021 nS. During the horizontal retrace
the video cycles would not be used and so are given back to the
processor (except for the last, which is used to generate sound and to
control the floppy drive speed). During the vertinal retrace all cycles
belong to the processor, except for the sound ones.

[drawing with SYSCLK, PCLK, original cycle and turbo cycle waveforms]

    We can see that the memory cycle now takes up only half the time
that it did before. This only was possible due to the evolution of the
technology for dynamic memory chips: the 4164-15 originally used needed
a cycle of at least 300 nS, while the 41256-12 has a cycle of 230 nS.
The increase in performance of the Turbo relative to the original design
comes from the possibility of having the memory sending more information
to the processor in the same time period. At first glance it might seem
that we can extract three times as much from memory, but

----
page 3

looking at the duration of a processor cycle we see that it can't use
two successive memory cycles. This and the fact that during the retraces
and access to ROM the processor is the limiting factor reduces the gain
in performance to about 20 to 30%.
   Let us look at the waveforms generated by the first PAL, which we will
call here "Timing State Machine" ou PAL0. It is the VCLK that defines the
basic cycles, but let's examine each part:

[drawing with SYSCLK, PCLK, Q1, Q2, VCLK, S1 and VSHFT waveforms]

    SYSCLK is generated directly from the 15.6672MHz oscillator and all
other clocks are derived from it. But PCLK is generated in PAL4 and is
used directly by the processor. Q1 has a cycle of 255 nS, since it is
PCLK divided by 2. This signal defines the memory cycles in the Turbo
Mac. Next we find Q2 and VCLK, which together with Q1 and PCLK form a
sort of counter. It is obvious that these signals are not all in the
same phase. VCLK and Q2 are three clocks early relative to the memory
signals. The reason for this will become clear when VSHFT is explained.
These two signals divide the basic cycle into four memory cycles. The
memory cycle where Q2 is high and VCLK is high is reserved for video.
The negative edge of VCLK, which happens halfway through this cycle,
increments the video counters. When we look at CASH and CASL next, it
might seem that the falling edge of VCLK would change the video address
before the hold time (though only in the worst case considering component
tolerances) but this doesn't happen because the column address for video
comes from the most significant bits of the counter which are incremented
by RESNYB.
------
all following pages are missing